** Eliyan Corporation:** is leading the chiplet revolution, focusing on a fundamental challenge with scaling semiconductor performance, size, power, and cost to meet the needs of high-performance computing applications, from desktop to datacenter. It has developed a breakthrough method to enable the industry’s highest performing interconnect for homogenous and heterogenous multi-die architectures using standard packaging substrates, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. The company’s Bunch of Wires (BoW) technique, invented by founder, Ramin Farjadrad, and proven to increase performance by 2x and reduce power in half in advanced process technologies, provides a more efficient approach to developing chiplet-based architectures - which are the pathway to the continued scaling of Moore’s Law.
Join the leading chiplet startup! As an Eliyan Analog/Mixed Signals Design Engineer, you will be working at a fast-paced early stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing various analog mixed signal blocks such as receiver, transmitter, and clock distribution. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
** Key Responsibilities:**
• Develop custom analog mixed-signal blocks for high-speed wireline links.
• Work closely with digital teams to implement and optimize mixed signal designs.
• Design, verify, and performs post-silicon validation and characterization of mixed-signal designs.
** Qualifications:**
• M.S. or Ph.D in Electrical Engineering
• Minimum two years experience designing high-speed SerDes components such as CTLEs,
Transmitter, Receiver, PLLs, etc.
• Direct experience designing in advanced CMOS (5nm or below) at data rates of at least 10Gb/s.
• Proficient with Cadence Virtuoso design environment and mixed-signal simulation (ADE,
Spectre).
• Solid understanding of high-speed layout considerations, such as parasitics, crosstalk isolation,
supply and bias distribution.
• Silicon bring-up, debug, and evaluation.
• Hands on layout experience a plus
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