Stanford, California
The company is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Their history is one of pushing the boundaries in the high-performance FPGA market. Offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all products.
Job Description/Responsibilities
The employee will invent, devise, and implement robust software solutions for placement and routing of large FPGAs, leveraging unique features of our FPGA technology. The employee will utilize his/her knowledge of electronic design automation (EDA) algorithms in the context of a high-performance timing-driven FPGA placement and routing and will make significant contributions to the ACE software tool chain.
The employee will primarily be responsible for inventing, designing and implementing novel FPGA placement and routing algorithms in our software tool chain. The candidate will be an expert in the area of EDA for VLSI. The candidate will have a unique opportunity to collaborate directly with other Research and Development (R&D) Software team members working on synthesis, detailed routing, global routing, detailed placement, global placement, timing improvements, runtime analysis, runtime and memory optimizations, and continuously improve quality of results.
Required Skills
Preferred Skills
Experience and Education
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